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T1: Random matching and layout induced mismatch effects


09:30 - 11:00

room 3


Jeroen van Beurden

In 1999 I got a master’s degree in theoretical physics at the University of Nijmegen, The Netherlands. After working in the IT sector for several years, I started working in the device modeling group at NXP Semiconductors in Nijmegen in 2007. The last four years I have specialized in the fields of flicker noise and mismatch. My activities include (but are not limited to) specification of test-structures, doing characterization measurements for flicker noise and mismatch, processing and analyzing measurement results and verifying / modifying models to match these measurements.


Variability of semiconductor device performance is one of the toughest circuit design challenges on the “more Moore” shrink path for advanced CMOS technologies.

Random effects related to microscopic device architecture fluctuations become more severe with reducing device dimensions while more random parametric variability sources are emerging. On top of this, parametric variations across a wafer or process variation from wafer-to-wafer or lot-to-lot contribute significantly to variability.

Next to these, from a circuit designer’s perspective, unavoidable sources of variation, there are avoidable sources of device differences that become manifest as systematic offsets in high-precision circuits. Avoiding such  is a matter of good design and layout discipline.

This tutorial addresses both the unavoidable (random) sources of mismatch and the avoidable systematic mismatch hazards.

We will provide orders of magnitude and rules of thumb for random mismatch for different types of semiconductor devices and summarize guidelines on how to analyze and cope with avoidable and unavoidable variability.



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