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T3: System Technology Co-optimization for 3D integrated AI/ML SOC design


09:30 - 11:00

Auditorium B


Dwaipayan Biswas (imec Leuven, BE)

Dwaipayan Biswas received the M.Sc. degree in system on chip and the Ph.D. degree in electrical engineering from University of Southampton (UoS), Southampton, U.K., in 2011 and 2015, respectively. From 2015 to 2016, he was a Postdoctoral Research Fellow with UoS. In 2016, he joined IMEC, as a researcher on digital IC design for biomedical applications. Currently he is leading a team of 10 people comprising payroll, postdoc, and PhD, responsible for managing the System Technology Co-optimization (STCO) program at IMEC, Leuven, Belgium. His current research focusses on exploring the interception of imec’s advanced semiconductor technology on future compute system challenges. He has authored several peer-reviewed journals, conferences, and edited a book. His research interests include low-power VLSI design, advanced technology for system optimization.

Dragomir Milojevic (imec Leuven, BE)

Dragomir Milojevic received his M.S. and PhD degrees in Electrical Engineering from Université libre de Bruxelles (ULB), Belgium, where he holds the position of professor of digital electronics and digital systems design. In 2004 he joined IMEC, where he first worked on multiprocessor and Network-on-Chip architectures for low-power multimedia systems. Since 2008 he has been working on design enablement for 3D stacked integrated circuits. Today, part of STCO & 3D programs at IMEC, he is working on system and design technology co-optimization of advanced technology nodes and design methodologies and tools for technology aware design of 3D integrated circuits. Dragomir Milojevic authored or co-authored more than 100 journal and conference articles and served as technical program committee member to several conferences in the field.


In the ever-evolving technology landscape, the advent of denser technologies has become a catalyst for unprecedented innovation. Technology scaling funneled by logic, memory and 3D enable higher compute, memory and bandwidth density and hence is a key factor towards scalable system architecture design. In the more than Moore era, system-technology co-optimization (STCO) is a promising paradigm for leveraging the synergy between emerging technology and application-driven architectures to achieve higher efficiency and performance at cost parity. As artificial Intelligence (AI) and Machine Learning, continues to advance and become more integrated into various industries, there is a growing need for joint optimization across the stack-workloads-architecture-design and technology.


In this talk, we look at 3D technology driven STCO for diverse AI/ML system architectures to answer the bandwidth and memory wall challenges. We start by looking at different technology offerings for 3D interconnects in conjunction with functional partitional of the design. This includes Face-to-Face (F2F) integration using fine-pitch W2W-hybrid copper-to-copper bonding constrained to two dies and Face-to-Back (F2B) multitier stacking using through-silicon-via (TSV). Next, we explore the impact of such technologies on diverse AI inference architectures – high performance edge, neuromorphic and general-purpose RISC-V, with an aim towards on-chip memory expansion, footprint reduction and low-power design. This is coupled with workload aware design space exploration (DSE), considering advanced logic technology, heterogenous embedded memory hierarchy (SRAM + MRAM) and 3D EDA enabled PnR based block-level PPA metrics. Lastly, as power density continues to rise with technology scaling, we cover thermal impacts for High Performance Computing (HPC) systems and low-power 3D stacks. Thermal analysis includes a complete package layer definition including Thermal Interface Material (TIM) choices, 3D stacking options, backside power delivery networks and strategies for cooling and thermal hotspot mitigation.



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