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W11: Pushing the power efficiency of data-converters and their limits

 

14:00 - 17:30

Auditorium B

chairs

abstract

The trend to surround us with ubiquitous data processed by artificial intelligence and spatial-temporal emphasis on communication and sensing requires ever increasing number of data-converters present in state-of-the-art ICs. This requires mastering various data-converter architectures while pushing the limits of bandwidth and dynamic range while aggressively reducing power dissipation. This challenge becomes even more demanding as speed of the transistors provided by the most advances process nodes are limited by the back-end parasitic, which requires parasitic aware ADC architecture innovations. This workshop covers the most recent innovations in ADC architectures and explore their limits in-terms of power efficiency and performance.

PROGRAM

The Rise and Rise of Continuous-Time ADCs

Shanthi Pavan

Every ADC should be preceded by an anti-alias filter. Furthermore, circuit and system designers have long recognized the need for an ADC to be easily drivable. It turns out that continuous-time ADCs combine anti-alias filtering with ease of drivability. While continuous-time delta-sigma ADCs have been known to offer a resistive input impedance and inherent anti-aliasing, they are effective only at high oversampling ratios. The continuous-time pipeline ADC is a recent innovation that offers these benefits at low OSRs. This talk will discuss the benefits and challenges of CTPs and CTDSMs, and present case studies demonstrating these benefits.

 

Design Techniques for Energy-Efficient ADCs

Youngcheol Chae

The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best-reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this talk discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.

The Evolution, Tradeoffs and Future of Noise-Shaping SAR

Michael P. Flynn

The Noise-Shaping SAR is a relatively new ADC architecture that combines the advantages of SAR and delta-sigma. It is particularly energy-efficient compared to delta-sigma and better suited for higher resolution compared to SAR. While the first noise-shaping SAR ADCs were limited to moderate resolution and speed, recent developments have extended the SNR to audio performance levels using high-order noise shaping. On the other hand, interleaving of noise-shaping SAR has effectively addressed the speed bottleneck. Noise-shaping SARs are also useful in hybrid ADCs where they can efficiently increase the order of a continuous-time delta-sigma as a backend quantizer. This presentation provides an overview of the noise-shaping SAR's evolution, discusses essential tradeoffs, and looks at what the future may hold.

 

Massive Time-Interleaving for realizing compact extreme high-speed ADCs

Ewout Martens

Realizing extreme high sampling speeds for ADCs require interleaving several channels. In this presentation, the limits are explored for architectures that utilize massive time-interleaving of a huge number of low-speed compact channels rather than of a small number of high-speed channels. By maximizing the conversion per area, the impact of interconnection parasitics is minimized leading to a power- and area-efficient solution for next-generation extreme high-speed ADCs with moderate resolution. This concept is illustrated with an implementation of a 16nm ADC that interleaves 768 slope ADCs to obtain an overall sampling speed of 42GS/s.

 

biosketches

Shanthi Pavan

Shanthi Pavan is currently the NT Alexander Institute Chair Professor of Electrical Engineering at IIT Madras. He is the author of Understanding Delta-Sigma Data Converters (second edition, with Richard Schreier and Gabor Temes), which received the Wiley-IEEE Press Professional Book Award for the year 2020. His research interests are in high-speed analog circuit design and signal processing. Dr. Pavan is a fellow of the Indian National Academy of Engineering, and the recipient of several awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award in 2009. He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems—I: Regular Papers and  as a DL of the IEEE Circuits-and-Systems Society.  He is a two-time Distinguished Lecturer of the IEEE Solid-State Circuits  Society.  He currently serves as the Vice-President of Publications of the IEEE Solid-State Circuits Society, on the Technical Program Committee of the International Solid-State Circuits Conference (ISSCC), and on the editorial board of the IEEE Journal of Solid-State Circuits. He is an IEEE Fellow.

Youngcheol Chae

Youngcheol Chae is currently a Professor in Electrical and Electronic Engineering at Yonsei University, Seoul, Korea. He received his B.S., M.S., and Ph.D. degrees from Yonsei University in 2003, 2005, and 2009, respectively. From 2009 to 2011, as a post-doctoral researcher at Delft University of Technology in the Netherlands, he developed high-precision sensors and interface ICs. After joining Yonsei University in 2012, he leads a Yonsei Mixed-Signal IC group, focusing on innovative analog and mixed-signal circuits and systems for communication, sensing, and biomedical applications. This has resulted in 130+ peer-reviewed journal and conference papers and holds 50+ patents. Especially, his research team reported 20 State-of-The-Art Chips at the International Solid-State Circuits Conference (ISSCC).

Dr. Chae has been serving as a TPC member of the International Solid-State Circuits Conference (ISSCC), Asian Solid-State Circuits Conference (A-SSCC), and Custom Integrated Circuits Conference (CICC). He received the ISSCC 2021 Takuo Sugano Award for Outstanding Far-East Paper, the Best Young Professor Award in Engineering from Yonsei University in 2018, the Haedong Young Engineer Award from the Institute of Electronics and Information Engineers (IEIE) Korea in 2017, the ISSCC Silkroad Award in 2017, the Outstanding Research Award of Yonsei University (2017, 2019, and 2020), and the Outstanding Teaching Awards of Yonsei University (2013, 2014). He was a guest editor of the Journal of Solid-State Circuits (JSSC) and a distinguished lecturer (DL) of IEEE Solid-State Circuits Society (SSCS).

Michael P. Flynn

Michael P. Flynn is the Fawwaz T. Ulaby Professor of Electrical and Computer Engineering at the University of Michigan. Michael Flynn is a 2008 Guggenheim Fellow and an IEEE Fellow. He received the 2023 IEEE Brokaw Award for Circuit Elegance. Dr. Flynn was Editor-in-Chief of the IEEE Journal of Solid-State Circuits from 2013 to 2016. He is a former Distinguished Lecturer of the IEEE Solid-State Circuits Society. He was chair of the Data Conversion Committee of the International Solid-State Circuits Conference.

 

Ewout Martens

Ewout Martens received the M.Sc. degree in electronic engineering in 2001 and Ph.D. degree (summa cum laude) in 2007 from the Katholieke Universiteit Leuven, Belgium. From 2007 to 2010, he worked in a spin-off company of KU Leuven as Chief Scientist focused on analog design automation. He joined imec, Belgium, in 2010 and is currently working as Principal Member of Technical Staff focused on research and design of next-generation high-speed data converters. He authored and co-authored more than 50 publications at international conferences and journals, and served as technical program committee member of the Symposium on VLSI Circuits from 2017 to 2020

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