W5: MOS-AK: Compact Modeling Support for OpenPDK and FOSS IC Designs
09:30 - 13:00
room 3
chair
Wladek Grabinski (MOS-AK, CH)
abstract
MOS-AK workshop discusses the frontiers of the compact models which are the core of reliable PDKs for the advanced semiconductor technologies. However, the semiconductor industry facing the workforce challenges, particularly in retaining skilled technicians and engineers. To meet the global demand, the FOSS CAD/EDA tools with the recently available open access PDKs provide a new platform to connect IC design beginners, enthusiasts and experienced mentors to benefit from the fast-growing open-source IC design movement. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern compact models in OpenPDKs with the open source analog/RF and digital IC examples.
program
9:30 - 9:40
Welcome and introduction to MOS-AK
Wladek Grabinski (MOS-AK, CH)
9:40 - 10:00
The IHP OpenPDK Initiative
Rene Scholz (IHP, DE)
In this presentation, we will present the current status and future roadmap for the development of the IHP Open Source Process Design Kit. We will give an overview of the ongoing projects and a timeline for new features such as PDK support for open source Radhard and RF designs. In addition, we will present a schedule for access to free design area in IHP Multi project wafer runs and explain the conditions and procedures for this. We will also give an outlook on how special offers for access to IHP open source
technology can be maintained.
10:00 - 10:20
Overview and Latest Updates of PSP and L-UTSOI Standard Model
Sebastien Martinie (CEA-Leti, FR)
In this presentation, we describe latest PSP [1] & L-UTSOI [2] developments, standard compact models [3] dedicated respectively to bulk and FDSOI technologies. Used in industrial Process Design Kits for years, these models is a highly mature and its strong physical background makes it very accurate and predictive. For PSP model, we presents the recent major release 104.0 which introduced some key feature such as: improvement of charge model calculation for short channel, new DIBL model based on a quasi-Fermi level correction including screening effect in inversion regime, improvement of S/D symmetry based on C∞ function, new binning equation with “hybrid” approach… For L-UTSOI model, we present the recent release 102.7 which introduced some key feature around improvement of robustness of the model in regards to cryogenic temperature: introduction of new potential reference shift from the source intrinsic energy level to the source conduction band energy level, introduction of band tails effect through with low temperature subthreshold slope saturation model
10:20 - 10:40
A Review of Charge-Based MOS Transistor Modeling - An Engineering and Educational Tool
Matthias Bucher (TU Crete, GR)
The charge-based model of the MOS transistor is a highly versatile tool in circuit design and engineering education. The model clarifies relationships among key circuit-design Figures-of-merit (FoMs) such as transconductance, transconductance-to-current ratio, self-gain, capacitance, gain-bandwidth (GBW), noise and mismatch. All these quantities are directly related to the mobile charge in the MOS channel. Simple parameter extraction procedures will be discussed. Analytical equations and a minimal parameter set allow one to express the design quantities continuously in all operating regions, from weak through moderate and strong inversion. The model is a highly valuable tool in educating analog design engineers. Finally, some application examples, including related to recent open-source PDKs, will be presented.
10:40 - 11:00
Value and Opportunities in Open-Source for Circuit Design
Christoph Sandner (Infineon, AT)
Recently, open-source initiatives for chip design and EDA methodology are picking up momentum and see a quickly growing community. In this talk some considerations will be given about the reasons behind this growth, the potential value for both research/academia and Industry, as well as opportunities of OS usage
11:00 - 11:30
Coffee break
11:30 - 11:50
OpenEMS as a Versatile Tool in the Framework of Mm-Wave OpenPDK-Based RF Chip Design
Mustafa Alchalabi (Uni. Duisburg-Essen, DE)
The release by IHP-GmbH in September 2023, of a Process Design Kit (PDK) specification for a 130nm iCMOS process provides IC designers access to an open source PDK for analog, digital mixed signal and RF IC design. An important goal of the IHP project is to provide PDK, and related data, that are freely available for creating manufacturable designs at IHP’s facility based on FOSS software. The open access Qucs-S circuit simualtion package has been selected by IHP as a central tool in the IC design sequence. This presentation outlines the background and the IHP PDK capabilities currently implemented with Qucs-S, Ngspice and OpenVAF. The recent release of Qucs-S version 24.2.0 further expands the tool set to include RF microstrip layout and analysis, using the Qucs-RFlayout and openEMS software. Throughout the presentation, a series of simulation examples are introduced. These demonstrate the application of Qucs-S in analog, mixed mode analog/digital and RF design. All the software introduced in this talk is freely available and can be downloaded using the internet links provided.
11:50 - 12:10
QUCS-S - A Central Tool in the OpenPDK IC Design Flow
Mike Brinson (LondonMET, UK)
The release by IHP-GmbH in September 2023, of a Process Design Kit (PDK) specification for a 130nm BiCMOS process provides IC designers access to an open source PDK for analog, digital mixed signal and RF IC Design. An important goal of the IHP project is to provide PDK, and related data, that are freely available for creating manufacturable designs at IHP’s facility based on FOSS software. The open access Qucs-S circuit simualtion package has been selected by IHP as a central tool in the IC design sequence. This presentation outlines the background and the IHP PDK capabilities currently implemented with Qucs-S, Ngspice and OpenVAF. The recent release of Qucs-S version 24.2.0 further expands the tool set to include RF microstrip layout and analysis, using the Qucs-RFlayout and openEMS software. Throughout the presentation, a series of simulation examples are introduced. These demonstrate the application of Qucs-S in analog, mixed mode analog/digital and RF design. All the software introduced in this talk is freely available and can be downloaded using the internet links provided..
12:10 - 12:30
Designing Analog/RF Chips Using Open PDKs and Open-Source Tools
Harald Pretl (JKU, AT)
During this presentation, we will examine the driving factors behind the growing popularity of open-source integrated circuit (IC) design tools. Additionally, we will explore the current state of these tools and the recently introduced open-source process design kits, with a specific emphasis on analog, mixed-signal, and radio frequency (RF) applications. We will present a meticulously selected collection of electronic design automation (EDA) tools and discuss their utilization in a mixed-signal circuit design flow. Furthermore, we will highlight recent advancements that have been made possible through the collaborative nature of open-source projects. Lastly, we will encourage collaborative efforts and discuss areas in which contributions to these projects are needed.
12:30 - 12:50
Are Open Source Digital Design Flows Ready for Mainstream?
Frank K. Gurkaynak (ETHZ, CH)
In this talk we summarize the state of open source design flows for digital design based on our own experience of taping out Linux capable 64-bit RISC-V SoCs using IHP 130 openPDK. While there are some challenges, we show that complete open source flows from RTL to GDS is at a more advanced state than what most people realize and highlight what aspects needs more support from the community.
12:50 - 13:00
Conclusion
biosketches
Rene Scholz
Dr. René Scholz received his PhD in physics from the Martin Luther University Halle-Wittenberg in 1999. He is group leader of IHP’s Research & Prototyping Service since 2004. His group is responsible for the organization of the MPW service and the development of process design kits for IHP’s BiCMOS technologies. In 2008, he earned an MBA - Management for Central and Eastern Europe from the European University Viadrina Frankfurt (Oder). He has background in HBT spice modeling and RF measurements. Recently, he actively contributes to projects driving the development of open source PDK in IHP BiCMOS technologies.
Sebastien Martinie
Sébastien Martinie received the M.S. degree in electrical engineering from the École Polytechnique Universitaire de Marseille, Marseille, France, in 2006, and the Ph.D. degree from the University of Aix-Marseille, Marseille, in 2009., he has been with CEA, Leti, Grenoble, France, since 2012, as a Research Engineer. In CEA-Leti compact modeling team, He is in charge of part of the development of the L-UTSOI and PSP standard models. He has authored or co-authored over 100 papers and communications.
Matthias Bucher
Matthias Bucher received the Diploma in Electrical Engineering and the PhD from EPFL, Lausanne, Switzerland, in 1993 and 1999, respectively. In 2004, he joined the faculty of Electrical & Computer Engineering School of the Technical University of Crete (TUC), Chania, Greece, where is a Full Professor. He was a Visiting Researcher with LSI Logic, Inc., Milpitas, California, in 1997, and a postdoctoral Researcher at the National Technical University Athens (NTUA) from 2000 to 2003. In 2014, he co-founded weasic microelectronics SA, in Athens, Greece, a company developing IP in RF transceiver front-ends. He has published over 140 papers in journals and international conference proceedings. His research interests are in low-power, low-voltage, analog/RF integrated circuit design, and in advanced compact modeling and characterization techniques for nanoscale electron devices, including compound semiconductors such as GaN HEMTs and SiC MOSFETs. He is the initiator and main developer of the EKV3 MOS transistor compact model. He has held consulting mandates in microelectronics industry and research organizations such as CERN.
Mike Brinson
Mike Brinson received a first class honours BSc degree in the Physics and Technology of Electronics from the United Kingdom Council for National Academic Awards in 1965, and a PhD in Solid State Physics from London University in 1968. Since 1968 Dr. Brinson has held academic posts in Electronics and Computer Science. From 1997 till 2000 he was a visiting Professor of Analogue Microelectronics at Hochschule, Breman, Germany. Currently, he is a Professor at the Centre for Communication Technology Research, London Metropolitan University, UK. He is a Chartered Engineer (CEng) and a Fellow of the Institution of Engineering and Technology (FIET), a Chartered Physicist (CPhys), and a member of the Institute of Physics (MInstP). Prof. Brinson joined the Qucs project development team in 2006.
Mustafa Alchalabi
Mustafa Alchalabi completed his Master's thesis at the University of Duisburg-Essen, June this year, where he was focusing on the development of ultra-broadband metamaterial antennas for MRI applications at the high magnetic field up to 7T. Mustafa's research involved extensive use of FDTD simulations. As of 1st September, he is part of the DI-DEMICO project, working on the further development of openEMS for IHP's openPDK. Through his Master's thesis, Mustafa has gained expertise in computational electromagnetics and its practical applications in medical technology and RF systems.
Christoph Sandner
Christoph Sandner (IEEE member S‘93-M’95-SM’13) was born in Munich, Germany, in 1968. He received the Dipl.-Ing. degree in electrical engineering from the Technical University of Graz, Austria, in 1995. Since graduation, he has been with the Microelectronics Development Center of Siemens AG, now Infineon Technologies, in Villach, Austria. His current focus is on innovations for R&D methodology, specifically on analog circuit generators. He was/is member of the technical program committee of several IEEE conferences, including ISSCC, VLSI Symposium and others. He is member of the ESSERC conference steering committee. He holds more than 20 patents and is author or co-author of more than 50 papers in nternational journals and conferences.
Harald Pretl
Harald Pretl received a Dipl.-Ing. degree (with distinction) in electrical engineering from the Graz University of Technology, Austria, in 1997, and the Dr. techn. degree from the Johannes Kepler University (JKU) in Linz, Austria, in 2001. From 2000 to 2011, he worked at Infineon Technologies as Director and Senior Principal Engineer, from 2011 to 2019 at Intel as Senior Principal Engineer and Chief RF Technologist, and from 2019 to 2022 at Apple, contributing to several generations of cellular RF transceivers. Since 2015, he has been a full professor, heading the Institute for Integrated Circuits (IIC) at JKU. He maintains the IIC-OSIC-TOOLS and is a member of the IEEE SSCS TC-OSE. He is currently a visiting researcher at IHP Microelectronics. In 2023, Harald founded PRETL consult GmbH, providing consulting services in the area of IC design.
Frank K. Gurkaynak
Frank is a senior scientist at ETH Zurich in the group of Prof. Luca Benini and has been involved in the PULP platform project (https://pulp-platform.org/) since its start in 2013. He also leads the Microelectronics Design Center (https://dz.ethz.ch/) which supports IC Design flows at ETH Zurich. His research interests include digital design, computer architectures and open source hardware.