top of page


The first European Solid-State Device Research Conference (ESSDERC) conference was organized in 1971 in Munich, Germany, aiming to present the latest developments in physics, technology and characterization of solid- state devices and bringing together both the academic world and the industry active on silicon and compound semiconductor integrated circuits.

In 1975, the initiative was taken to start up a sister conference, European Solid-State Circuits Conference (ESSCIRC) focusing on recent advances in design concepts, design methodologies, circuit simulation and solid-state circuits. Since the last decade there is a worldwide trend towards education, academic research and industrial development that strengthens the link between device technology and circuit design. This stems from the need to reconcile system, circuit and technology R&D in a world that needs ever more advanced, complex applications implemented in ever more advanced, powerful technologies. Consequently, Designers and technologists must closely collaborate. Only when both disciplines and skills go hand in hand, optimal solutions will be achieved. To cope with this important trend, the ESSDERC/ESSCIRC Steering Committee (EStC) recently decided to reorganize the conferences into a single conference format under a new name.

The last ESSDERC/ESSCIRC conference took place in Lisbon, Portugal, September 11-14, 2023.

The first “European Solid-State Electronics Research Conference - ESSERC” is scheduled for Bruges, Belgium, September 9-12, 2024.

The historical link with both ESSDERC and ESSCIRC remains and is also reflected in the new logo and the fact that the conference in Bruges will be referenced as the 50th ESSERC Conference. ESSERC has a single Technical Program Committee, a coordinating Steering Committee, a Conference Chair and Co-Chair and three Track Chairs, i.e., one for Circuits, one for Technologies and one for a Joint Track.

The aim of ESSERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary.


The conference format is four days, running from Monday to Thursday:

  • Monday: Tutorials and Workshops

  • Tuesday-Wednesday-Thursday: Technical sessions

Besides the lunches and coffee breaks, the social activities include a Welcome Cocktail on Tuesday evening and a Gala Dinner on Wednesday evening.

The Conference technical program includes: 

  • 9 keynote presentations on circuits/design aspects, semiconductor technology and joint technologies and devices topics

  • A grand cru selection of research papers in the domains of IC design and semiconductor device development

  • Presentation of IEEE and ESSERC Awards

  • ESSERC Gala Dinner on Wednesday, September 11, 2024

  • Tutorials and Workshops

The venue of the conference events, including workshops and tutorials, will be in the center of Bruges (Bruges Meeting & Convention Centre -BMCC- Beursplein 1, 8000 Bruges).

The working language of the conference is English.


Papers submission deadline

April 5, 2024


Papers presented at the conference will be considered for the “Best Paper Award” and “Best Young Scientist Paper Award”. The selection will be based on the results of the paper selection process and the judgment of the conference participants. The award delivery will take place during ESSERC 2025.


  1. Advanced Technology, Process and Materials

  2. Analog, Power and RF Devices

  3. Compact Modeling and Process/Device Simulation

  4. Analog Circuits

  5. Data Converters

  6. RF & mm-Wave Circuits

  7. Frequency Generation Circuits

  8. Digital Circuits & Systems

  9. Power Management

  10. Wireless Systems

  11. Wireline and Optical Circuits and Systems

  12. Emerging Computing Devices and Circuits

  13. Architectures and Circuits for AI and ML

  14. Devices & Circuits for Sensors, Imagers and Displays

bottom of page